Method and apparatus for parallel midamble cancellation

ABSTRACT

Method and apparatus for performing midamble cancellation to remove midamble interference from the convolution tail of data field 1 and the first W-1 chips of the midamble field which results from the delay spread of the multipath channel and for canceling the first W-1 chip midamble spread in the data field 2, which operations are performed substantially simultaneously. The received burst, typically a TDD burst, is stored, the midamble interference and the corresponding parts in the received burst is removed and the resulting burst is applied to a multi-user detector to obtain the symbol sequences.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims priority from U.S. provisionalapplication No. 60/379,196 filed on May 9, 2002, which is incorporatedby reference as if fully set forth.

BACKGROUND

[0002] The present invention relates to midamble cancellation. Moreparticularly the present invention relates to method and apparatus forperforming midamble cancellation utilizing an algorithm enablingparallel cancellation of midamble for both data field 1 and data field 2of a received TDD burst.

[0003] As shown in FIG. 1, a burst is received through a multipathchannel having a time-delay spread of (W-1)*T_(c), where W representsthe number of chips and T_(c) represents chip duration. The time (delay)− spread channel causes inter-chip interference whereby the convolutiontail of each field in the received burst protrudes upon the adjacentfield. For example, the midamble inter-chip interference on the firstW-1 chips of data field 2 may cause performance degradation of the dataestimation procedure of the symbols corresponding to the first W-1chips, unless a remedy for the interference is considered. This isespecially true since the transmit power control (TPC) command (inuplink (UL) only) and transport format combination indicator (TFCI) bitsare located immediately after the midamble and they are not protected byany channel coding scheme, it is desirable to eliminate midambleinterference by employing a midamble cancellation procedure to improvedata estimation for both data parts of the TDD burst and is astand-alone procedure that can be used to enhance performance of any ofthe candidate data estimation algorithms.

[0004] Midamble cancellation (also referred to hereinafter as MDC) canalso be applied to remove midamble interference from the convolutiontail of Data field 1 into the first (W-1) chips of the midamble field,also shown in FIG. 1. This tail also results from the delay spread ofthe multipath channel and its inclusion into the data estimation of Datafield 1 results in more observed data and leads to an exact blockToeplitz structure of the A^(H) A matrix in multi-user detection (MUD).

SUMMARY

[0005] Midamble cancellation is used to remove the effect of themidamble from:

[0006] The first W-1 chips of the midamble field, allowing bettermodeling of the convolution tail of the first Data field protruding intothe midamble field, further allowing modeling of the A^(H) A matrix tobe exactly block Toeplitz; and the first W-1 chips of Data field 2. Atechnique is provided for calculation of midamble interference whichsignificantly reduces the necessary hardware as well as processing time.

BRIEF DESCRIPTION OF THE DRAWING(S)

[0007] The invention will be understood from the accompanying figures,wherein like elements are designated by like numerals and, wherein:

[0008]FIG. 1 shows a transmitted burst, a channel and a received burst(TDD DPCH) which is useful in explaining the need for midamblecancellation.

[0009]FIG. 2 is a block diagram of data demodulation circuit for a basestation, (BS) including a midamble cancellation block.

[0010]FIG. 3 is a block diagram of a data demodulation circuit for auser equipment (UE) similar to the BS circuit shown in FIG. 2.

[0011]FIG. 4 is a block diagram showing a circuit for midamblecancellation utilizing the cancellation algorithm of the presentinvention.

[0012]FIG. 5 is a simplified block diagram of a midamble cancellationengine.

[0013]FIG. 6 is a block diagram showing one of the processing elementsof FIG. 5 in greater detail.

[0014]FIG. 7 is a block diagram showing how the midamble cancellationblock interfaces with other circuits of the system.

[0015]FIG. 8 is a graphical representation of the manner in whichprocessing of midamble sequences of the data fields are combined.

[0016]FIG. 9 is a block diagram of a midamble cancellation deviceembodying the principles of the present invention.

[0017]FIG. 10 is an illustration useful in explaining a processingelement calculation.

[0018]FIG. 11 is an illustration useful in explaining how a processingbreakdown can be managed.

[0019]FIG. 12 is an illustration useful in explaining the manner inwhich midamble shifts of Burst Type 2 are performed.

[0020]FIG. 13 is a simplified diagram showing the midamble cancellationprocessing timeline.

[0021]FIG. 14 is a simplified flow diagram of the midamble cancellationprocess.

[0022]FIGS. 15 and 16 respectively show preload and preprocessor statetransition diagrams.

[0023]FIG. 17 is a processing element state transition diagram.

[0024]FIG. 18 is a midamble shift state transition diagram.

[0025]FIG. 19 is a midamble data packer state transition diagram.

[0026]FIG. 20 is a data output state transition diagram

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

[0027]FIG. 2 is a block diagram showing a data demodulation circuit 10for demodulation of a TDD burst employed at a base station (BS). Circuit10 includes a Steiner channel estimator 12 receiving a midamble portionof the burst. A midamble cancellation circuit 14 receives the TDD burstincluding data parts, midamble and the guard interval. The output ofchannel estimator 12 is applied to the post processing and midambledetection circuit 16 which develops channel responses at 16 a, which areapplied to the midamble cancellation circuit, and midamble shift numbersat 16 b which are likewise applied to the midamble cancellation circuit14.

[0028] The midamble shift numbers at 16 b are also applied to codedecision circuit 18 for determining channelization codes, provided at 18a, which are then applied to the multi-user detector (MUD) 20. Midamblecancellation circuit 14 utilizes the inputs described hereinabove forgenerating a midamble cancelled burst at 14 a which is applied to themulti-user detector circuit 20.

[0029] As can clearly be seen, midamble cancellation is implementedbefore MUD processing. The midamble cancellation procedure initiallyconstructs an estimate of the first W-1 chips of the midamble receivedin the midamble field and the first W-1 chips of the midamble spreadinto data field 2, respectively. The received midamble estimation isderived based on the channel responses provided by the channelestimator, 12 which utilizes a known algorithm for obtaining channelestimation, and midamble shift numbers obtained from the midambledetection block 16, which likewise uses a known algorithm to derivemidamble shift numbers which, in turn, are utilized to derivechannelization codes by code decision circuit 18 employing a knownalgorithm.

[0030] The received burst is stored in a buffer 32 which cooperates withthe algorithm 30 of FIG. 4, performed by the midamble cancellationcircuit 14 of FIG. 2, for example. The midamble interference fromcorresponding parts in the received bursts is removed. The resultingburst is fed into the MUD 20 shown in FIG. 2. The concept employed formidamble cancellation is the estimation of midamble interferenceaccording to acquired midamble shift numbers and channel responsesderived from detection circuit 16, whereupon the estimated interferenceis used to cancel the effective midamble interference from the receivedburst.

[0031] Midamble cancellation is applied separately to the even and oddsamples of the received over-sampled sequences.

[0032]FIG. 3 shows data demodulation circuit 11 employed by a userequipment (UE), wherein like elements as between FIGS. 2 and 3 aredesignated by like numerals and including the midamble cancellationblock and differs from FIG. 2 in that the output 14 of cancellationcircuit 14 is coupled to detection circuit 18 and blind code detectioncircuit 18, which provides detected midamble shifts 18 b to MUD 20, inaddition to the channelization codes.

[0033] The data employed in the cancellation circuitry of the presentinvention comprises:

[0034] The data inputs include a received data burst denoted by{overscore (r)} including both data parts, the midamble and the guardperiod: Type: vector of complex-values Length: 2560 chips Range:Unrestricted

[0035] K_(m) sets of complex channel coefficients:

[0036] [{{right arrow over (h)}¹, {right arrow over (h)}², . . . ,{right arrow over (h)}^(K) ^(_(m)) } where {right arrow over(h)}^(i)=[h₀ ^(i),h₁ ^(i), h₂ ^(i), . . . , h_(w−1) ^(i)]] Type: vectorof complex-values Length: K_(m) × W Range: Unrestricted

[0037] K_(m) is the number of different midambles detected by themidamble detection algorithm in the post processing and midambledetection block 16 (see FIG. 2). W is the length of each channelresponse.

[0038] K_(m) midamble shift numbers: each number is used to generate acorresponding midamble code. Type: vector of integers Length: 1 × K_(m)Range: 1 to K_(m)

[0039] A microprocessor (not shown) forming part of the cancellationcircuit 14 provides the association between channel impulse response andmidamble shift (equivalent to midamble codes), which indicates whichchannel response belongs to which midamble shift (code).

[0040] The data outputs include:

[0041] Midamble cancelled data burst: Type: vector of complex-valuesLength: 2560 chips Range: Unrestricted

[0042] The parameters of the algorithm are:

[0043] Maximum midamble shift K.

[0044] Length L of each midamble code.

[0045] Burst type in use.

[0046] Length W of channel responses where W=28, 32, 57, 64 or 114depending on the burst type and maximum midamble shift K.

[0047] Table 1 sets forth the values of the above parameters. TABLE 1Burst Burst Burst Burst Burst Para- type 1 type 1 type 1 type 2 type 2meter Description long nominal short nominal short K Maximum  64  8  16 3 6 midamble shift W Length of each 114  57 28 or 29  64  32 channelresponse in chips L Length of each 512 512 512 256 256 midamble code

[0048]FIG. 4 illustrates the midamble cancellation algorithm. Thereceived data burst is stored in a buffer memory 32, so that themidamble interference effect on data estimation for both data field 1and data field 2 can be removed. The active midamble codes of length Lin the same time slot are derived according to the input detectedmidamble shift numbers applied at 34. The midamble codes are derivedusing conventional algorithms. Then two received midamble interferencesequences are constructed at 36, 38, based on K_(m) associated pairs ofthe channel responses and active midamble codes. The first midambleinterference corresponds to the first W-1 chip midamble received in themidamble field, which interferes with the convolution tail of the datafield 1 protruding onto the midamble field, as indicated previously inFIG. 1. The received (W-1 chips) midamble sequence, {overscore(M)}^(mid), of length W-1, appearing at 36 a, can be modeled byconvolving each channel response with a corresponding midamble code,such as $\begin{matrix}\begin{matrix}{{\overset{\_}{M}}^{mid} = {\sum\limits_{k = 1}^{Km}{{\overset{\_}{m}}^{k} \otimes {\overset{\_}{h}}^{k}}}} & {{{taking}\quad {the}\quad {first}\quad W\text{-}1\quad {samples}}} \\{= {\sum\limits_{{k =}\quad}^{K_{m}}{\sum\limits_{i = 0}^{W - 2}{m_{i}^{k} \cdot h_{n - i}^{k}}}}} & {{{{{for}\quad n} = 0},1,{2\quad \ldots \quad W\text{-}2}}}\end{matrix} & {{Equation}\quad (1)}\end{matrix}$

[0049] where m_(i) ^(k) represents the i-th element of the midamble,{overscore (m)}^(k), associated with midamble shift k. Note thatm^(−k) = [  [m_(o)^(k)m₁^(k)  …  m_(L − 1)^(k)]  .

[0050] {circle over (X)} denotes the convolution operator. In otherwords, the received midamble sequence is a superposition of the K_(m)convolutions between the active midamble codes and channel responses.Equation (1) can be rewritten in a matrix form as follows:$\begin{matrix}\begin{matrix}{\begin{bmatrix}{\quad W} & {\quad W} & \quad & {\quad W} & \quad \\\overset{}{\begin{matrix}m_{0}^{1} & 0 & 0 & \cdots & \cdots & 0 \\m_{1}^{1} & m_{0}^{1} & 0 & \cdots & \cdots & 0 \\m_{2}^{1} & m_{1}^{1} & m_{0}^{1} & 0 & \cdots & 0 \\\vdots & \quad & \vdots & \quad & \vdots & \quad \\m_{W - 2}^{1} & m_{W - 3}^{1} & \quad & \cdots & m_{0}^{1} & 0\end{matrix}} & \overset{}{\begin{matrix}m_{0}^{2} & 0 & 0 & \cdots & \cdots & 0 \\m_{1}^{2} & m_{0}^{2} & 0 & \cdots & \cdots & 0 \\m_{2}^{2} & m_{1}^{2} & m_{0}^{2} & 0 & \cdots & 0 \\\vdots & \quad & \vdots & \quad & \vdots & \quad \\m_{W - 2}^{2} & m_{W - 3}^{2} & \quad & \cdots & m_{0}^{2} & 0\end{matrix}} & \begin{matrix}\cdots \\\cdots \\\cdots \\\quad \\\cdots\end{matrix} & \overset{}{\begin{matrix}m_{0}^{K_{m}} & 0 & 0 & \cdots & \cdots & 0 \\m_{1}^{K_{m}} & m_{0}^{K_{m}} & 0 & \cdots & \cdots & 0 \\m_{2}^{K_{m}} & m_{1}^{K_{m}} & m_{0}^{K_{m}} & 0 & \cdots & 0 \\\vdots & \quad & \vdots & \quad & \vdots & \quad \\m_{W - 2}^{K_{m}} & m_{W - 3}^{K_{m}} & \quad & \cdots & m_{0}^{K_{m}} & 0\end{matrix}} & \quad\end{bmatrix} \times} \\{\quad {\begin{bmatrix}( {\overset{->}{h}}^{1} )^{T} \\( {\overset{->}{h}}^{2} )^{T} \\\vdots \\\vdots \\( {\overset{->}{h}}^{K_{m}} )^{T}\end{bmatrix} = \begin{bmatrix}M_{0}^{mid} \\M_{1}^{mid} \\M_{2}^{mid} \\\vdots \\M_{W - 2}^{mid}\end{bmatrix}}}\end{matrix} & {{Equation}\quad (2)}\end{matrix}$

[0051] where $\begin{pmatrix}{- i} \\h\end{pmatrix}^{T}$

[0052] represents the transpose of the row channel response vector,{overscore (h)}^(i), and ${\overset{\_}{M}}^{mid} = {\begin{bmatrix}{M_{0}^{mid}\quad} & {M_{1}^{mid}\quad} & \cdots & {M_{W - 2}^{mid}\quad}\end{bmatrix}\quad.}$

[0053] The matrix consists of some midamble elements for all the K_(m)midambles in the LHS of the above equation is of size (W-1)W•K_(m). TheLHS of say, the i-th row represents the sum of K_(m) convolutionsevaluated at the time instance of the i-th chip of the receivedmidamble. The k-th partition of each row in the midamble matrix consistsof that portion of {overscore (m)}^(k) which contributes to the midambleinterference. In addition, [{overscore (h)}¹{overscore (h)}² . . .{overscore (h)}^(km)]^(T) is of size K_(m) W×1 and represents the jointchannel estimate.

[0054] The second received midamble interference corresponds to thefirst W-1 chips of the received midamble tail into the data field 2where the tail results from the delay spread of the channel, and itcorrupts the first W-1 chips of the received data field 2 (see FIG. 1).

[0055] The procedure for constructing the midamble interference issimilar to that for the data field 1 set forth above. However, in thiscase the convolution tail of the midamble field spreads into the datafield 2. The midamble interference on the first W-1 chips of the datafield 2, ${\overset{\_}{M}}^{data2} = \begin{bmatrix}{M_{0}^{data2}\quad} & {M_{1}^{data2}\quad} & \cdots & {M_{W - 2}^{data2}\quad}\end{bmatrix}$

[0056] can be then modeled in a matrix form as follows: $\begin{matrix}\begin{matrix}{\begin{bmatrix}{\quad W} & \quad & {\quad W} \\\overset{}{\begin{matrix}0 & m_{L - 1}^{1} & m_{L - 2}^{1} & \cdots & \quad & m_{L - {({W - 1})}}^{1} \\0 & 0 & m_{L - 1}^{1} & \cdots & \quad & m_{L - {({W - 1})} + 1}^{1} \\0 & 0 & 0 & m_{L - 1}^{1} & \cdots & m_{L - {({W - 1})} + 2}^{1} \\\vdots & \quad & \vdots & \vdots & \quad & \quad \\0 & 0 & 0 & \cdots & 0 & m_{L - 1}^{1}\end{matrix}} & \begin{matrix}\cdots \\\cdots \\\cdots \\\quad \\\cdots\end{matrix} & \overset{}{\begin{matrix}0 & m_{L - 1}^{K_{m}} & m_{L - 2}^{K_{m}} & \cdots & \quad & m_{L - {({W - 1})}}^{K_{m}} \\0 & 0 & m_{L - 1}^{K_{m}} & \cdots & \quad & m_{L - {({W - 1})} + 1}^{K_{m}} \\0 & 0 & 0 & m_{L - 1}^{K_{m}} & \cdots & m_{L - {({W - 1})} + 2}^{K_{m}} \\\vdots & \quad & \vdots & \vdots & \quad & \quad \\0 & 0 & 0 & \cdots & 0 & m_{L - 1}^{K_{m}}\end{matrix}}\end{bmatrix} \times} \\{\quad {\begin{bmatrix}( {\overset{->}{h}}^{1} )^{T} \\( {\overset{->}{h}}^{2} )^{T} \\\vdots \\\vdots \\( {\overset{->}{h}}^{K_{m}} )^{T}\end{bmatrix} = \begin{bmatrix}M_{0}^{data2} \\M_{1}^{data2} \\M_{2}^{data2} \\\vdots \\M_{W - 2}^{data2}\end{bmatrix}}}\end{matrix} & {{Equation}\quad (3)}\end{matrix}$

[0057] After modeling the two midamble interference sequences byEquations (2) and (3), respectively, Equation (2) is cancelled from thefirst W-1 chips of the midamble field in the received stored data burst,{overscore (r)}, at 40, where, in the absence of noise, each of thefirst W-1 chips consists of the corresponding midamble chips and theconvolution tail of the data field 1, as seen in FIG. 1. Next themidamble interference effect on the data field 2 is removed, at 42, bysubtracting Equation (3) from the first W-1 chips of the data field 2 in{overscore (r)}. The resulting data burst is then considered as being aburst in which data estimation is not affected by the midambleinterference.

[0058] The output, at 42 a, is applied to MUD 20, see FIG. 2, togetherwith the output at 18 a, to derive the estimated symbol sequences,appearing at output 20 a.

[0059] The performance of the technique of the present invention isdependent on the accuracy of the channel estimation and midambledetection algorithm. With perfectly known channel responses, theimplementation should result in less than 0.1 dB degradation inresultant signal-to noise ratio.

[0060] Since the midamble cancellation processing (circuit 14—FIG. 3) iscompleted before data demodulation (with MUD circuit 20), the processingtime of midamble cancellation directly affects MUD related latency.Taking into account transmit power control (TPC) latency and especiallylatency in extracting raw TPC bits, latency of midamble cancellationprocessing should be less than 80≈0.03 timeslot.

[0061] Processing element (PE) adders perform a “multiplication” ofmidambles and channel responses as shown by “multiplier” 108 in FIG. 5.Each PE is provided with storage registers (i.e. accumulators) 104, 106for each cancellation vector. Multiplexer, 110 selects the propermidamble output cancellation as will be more fully explained herein.

[0062] The following is a high-level description of the system design.FIG. 7 illustrates how the midamble cancellation block 72 interfaceswith the other components of the system 70. During processing, themidamble cancellation block 72 has full access to the channel estimatesRAMs 74, 76 without contention from other processes. The channelestimates consist of 16-bit complex values with real and imaginarycomponents separated into 2 RAMs, 74, 76.

[0063] The midamble server 78 supplies 16-bit midamble sequences basedon the midamble number and midamble shift. Each sequence corresponds to16 1-bit values.

[0064] Channel Estimation (CHEST) 80 supplies configuration parametersthat control the functionality of midamble cancellation. Also, CHESTsupplies control signals that initiate midamble cancellation processing.

[0065] The computed interference sequences are stored into 2 pairs ofRAMs 82-84 and 86-88. Each pair consists of a real component 82, 86 andan imaginary component 84, 88. One pair is for the data field 1interference results and the second pair is for the data field 2interference results.

[0066] From Equation 2 and Equation 3, set forth above, we can see thatthe processing consists of a large matrix multiplication. The size ofthe left-hand matrix is (W-1)×W*Km. The size of the right-hand vector isW*Km×1. The total number of multiplies is (W-1)*W*Km. Since the size ofeach midamble sample is 1 bit, the implementation of the multipliers canbe simplified and implemented by a mux.

[0067] Based on Table 1, the worst-case number of multiplies occurs whenW=57 and Km=8, resulting in a total of 25,536 multiplies. Performingthese multiplies sequentially is unacceptable since the total number ofclock cycles equals the number of multiplies. Instead, it is necessaryto perform the multiplications for multiple rows in parallel byassigning a processing element (PE) to each row. The PE for each row canbe conveniently implemented using a multiply and accumulate function.The total processing time then will be (W-1)*W*Km/NPE, where NPE is thenumber of PE's.

[0068] The greatest savings in processing time are achieved when NPE=thenumber of rows=(W-1). The worst case processing time, in this case, isW*Km. This occurs when W=29 and Km=16 and results in 464 cycles. If theprocessing time requirement permits it, the number of PE's could be madeless than the total number of rows. The PE's could be allocated to a setof rows for part of the processing time and then reallocated to adifferent set of rows for the next part of the overall processing.

[0069] The approach set forth above assumes each of the equations (2)and (3) are processed separately and that the hardware will need to beduplicated for each of the equations. From Equation 2 and Equation 3 wesee that the first multiplicand matrix is upper-triangular while thesecond matrix is lower triangular. We can combine the two matrices intoa single matrix since there is no overlap between the two of them. Thisallows the processing of the two equations to be combined into onehardware process. FIG. 8 is a graphical representation of the combinedprocessing.

[0070] The additional hardware consists of two (2) accumulators in eachPE instead of 1, along with the associated control logic. Note that eachPE performs a multiply and accumulate across a given row sequentially.Therefore, during any given clock cycle, only one of the twoaccumulators will be active and it will accumulate the results foreither the upper triangular matrix multiply or for the lower one. By theend of a row, both accumulators have the results for both of the matrixmultiplies.

[0071] The amount of hardware required to implement this function isdirectly related to the amount of time available for processing and tothe bit widths used for the computations. Since the processing time andbit width requirements need not be firm, the design herein was chosen tobe parameterized.

[0072] The parameterization occurs in two different aspects. First, thebit widths are parameterized allowing easy scaling of the design.Second, the amount of hardware used in parallel is also a parameter. Thedesign is based on a basic processing element referred to as a PE. Thenumber of required PE's depends on how parallel the design needs to be.Therefore, the number of PE's in the design is parameterized.

[0073] Note from the Equation 2 and Equation 3 that column i+1 in thematrices, is equal to column i shifted down by 1 row. This allows asimple architecture that uses a shift register 94 (see FIG. 9) tocontrol the flow of the midamble data into the PE's. FIG. 9 is a blockdiagram of the midamble cancellation design.

[0074] In FIG. 9, there are 2 shift registers, an upper one 92 and alower one 94. The lower shift register 94 supplies midamble data to eachof the processing elements PE. The upper shift register supplies data tobe shifted into the lower register 94. Timing and control is exerted bycontrol circuit 102.

[0075] At the start of processing, the lower register 94 contains all ofthe data needed for the data field 1 calculation (lower triangularmatrix—see FIG. 8). The upper register progressively supplies data forthe data field 2 calculation (upper triangular matrix). At thecompletion of the processing, the lower shift register 94 contains allof the data needed for data field 2.

[0076] The size of the upper shift register 92 is fixed at 16 bits. Thesize of the lower shift register 94 is equal to the number of PE's andis therefore parameterized. The parameter can take on multiples of16-bits. Each stage of the shift register contains one binary bit (0or 1) which respectively control subtraction and addition operations.

[0077] Each shift register has a set of queue registers R that allowprocessing to be pipelined. The queue registers R are loaded with datafrom the next active midamble shift, by RAM 96 while the PEs processdata stored in the working shift register 94 from the current midambleshift.

[0078] Note that data retrieved from the midamble RAM 96 is packed into16-bit words before being stored into the shift registers 92,94.

[0079] As set forth above, FIG. 5 is a simplified, high-level diagram ofa PE in the midamble cancellation design. Note that there are twoaccumulators 104,106 however, some hardware is shared between the twoprocesses. The PE “multiplies” the channel response vector by a midamblerow at 108. The output selector controls the multiplexer 110 to selectthe contents of one of the accumulators 104, 106.

[0080] Since both the channel estimates and the midamble bits arecomplex-valued samples, the PEs need to perform complex arithmetic.However, a full multiplier is not necessary since the midamble valueconsists of a single bit.

[0081] According to 3GPP TS 25.221: m _(i)=(j)^(i)*m_(i) for all i=1, .. . , P

[0082] Therefore, the midamble sample represents 1 of 4 possible values:

[0083] 1+0j

[0084] 0+1j

[0085] −1+0j

[0086] 0−1j

[0087] The channel estimate consists of a multi-bit complex value A+Bj.

[0088] Therefore, multiplying the channel responses by the midamblesamples results in 1 of 4 possible outputs:

[0089] (A+Bj)(1+0j)=A+Bj

[0090] (A+Bj)(0+1j)=−B+Aj

[0091] (A+Bj)(−1+0j)=−A−Bj

[0092] (A+Bj)(0−1j)=B−Aj

[0093] From this we see that multiplication can be implemented with apair of muxes (multiplexers) 120, 122 and a pair of adders/subtractors124, 126, as shown in FIG. 6. The midamble bit value m_(i) at 128controls the sign of the input (i.e. whether the samples get added orsubtracted). The 2-bit phase at 130 controls how the inputs are muxedinto the PE. The PE is initialized at 132, loading zeros into theaccumulators 134, 136 through the multiplexers 131 each accumulating areal part REAL 1 and REAL 2 at 134 a and 134 b and an imaginary partImag. 1 and Imag. 2 at 136 a and 136 b for each of the interferencevalues, as shown at 36 and 38 in FIG. 4. Multiplexers 138 and 140respectively select one of the values Real 1, REAL 2 and Imag. 1 andImag. 2. Each value at the outputs of muxes 138, 140 is returned to theadder subtractors 124, 126 for the next addition/subtraction operation.

[0094]FIG. 10 graphically shows the matrix multiplication process andillustrates the role of a processing element in the midamblecancellation design. Each PE is assigned to a given row. It should benoted that each row contains data from both the lower-triangular and theupper triangular portions of the equations above. Therefore, theaccumulators of each PE respectively contain data field 1 and data field2 interference values at the end of the processing cycle for each row.

[0095] From a consideration of FIG. 8 it can be seen that a PE for thefirst row of the upper matrix U does not provide an output at that PEfor the midamble associated with the left-hand-most column whereas thereis an output at that PE for the left-hand most column of the first rowof the lower matrix L. The PE assigned to the first row provides anoutput for all of the remaining columns for the lower matrix L and nooutputs for the upper matrix U.

[0096] The pattern is repeated for each subsequent row wherein one morecolumn position for each row yields an output for matrix U and one lesscolumn position yields an output for matrix L until, at the last row,there are no outputs for matrix L and all columns of the last row yieldan output for matrix U.

[0097] For a given implementation of the MDC, the number of PE's may beless than the number of required calculations. In this case, the totalnumber of rows is subdivided into sections whose size is the number ofPE's. This is illustrated in FIG. 13. At the end of each processingstep, the output data must be written out before the next process stepbegins. The processing step is repeated until all data has beenprocessed. Note that the last processing steps may utilize less than thetotal number of PE's.

[0098] Table 2 shows the combined midamble matrix derived from combiningEquation 2 and Equation 3 for a given midamble shift. TABLE 2 CombinedMidamble Matrix 0 1 2 . . . W − 3 W − 2 W − 1 L − L − L − 0 0 L − 1 L −2 . . . (W − 3) (W − 2) (W − 1) L − L − 1 1 0 L − 1 L − 2 . . . (W − 3)(W − 2) L − . . . . . . 1 0 L − 1 L − 2 . . . (W − 3) W − 4 W − 4 . . .1 0 L − 1 L − 2 . . . W − 3 W − 3 W − 4 . . . 1 0 L − 1 L − 2 W − 2 W −2 W − 3 W − 4 . . . 1 0 L − 1

[0099] Note that the total number of midamble elements required for agiven midamble shift consists of 0 to W-2and L-(W-1) to L-1. Note alsothat since the midamble is repetitive, L-1 and 0 are contiguous.Therefore, the total elements required consist of a contiguous list fromL-(W-1) to W-2 . When a subset of the total rows is processed due to alimited number of PE's, the list of required elements remains contiguoussince only the start and end points are altered. Therefore, retrievingmidamble samples can be simplified by establishing a start point andsequentially retrieving data until all the required data has beenretrieved. This simplifies the midamble packer control logic.

[0100] In reality, midamble cancellation establishes the end point andretrieves samples in reverse order. This is because the lower triangularmatrix is processed first.

[0101] Note that the indices listed above are all relative to the basicmidamble offsets for a particular midamble shift. The absolute midambleindices are discussed below.

[0102]FIG. 12 shows an example of how midamble cancellation calculates amidamble sample for burst type 2. As stated above, MDC requests anentire basic midamble sequence (of length P) from the midamble server atthe start of processing and stores it in a local RAM. A specific user'smidamble consists of L samples of a cyclically shifted version of thebasic midamble.

[0103] MDC creates a shifted midamble sequence by addressing themidamble RAM in a circular fashion. The starting point is based on themidamble shift number.

[0104] Table 3 lists the equations from two (2) different versions ofthird generation (3G) specifications that define how to generate theinitial midamble offsets based on the basic midamble. Both versions areshown as a reference, depending on what version is used for Spin 1 ofthe design. Table 4 and Table 5 list the initial offset valuescalculated from the corresponding equations for both long and shortmidamble, respectively. TABLE 3 Equations to Calculate Midamble ShiftsFrom TS 25.221 v3.3.0 Eq. 1(K′ − k)W k = 1 to K′ Eq. 2(K − k)W +floor(P/K) k = K′ + 1 to K From TS 25.221 v4.1.0 Eq. 1(K′ − k)W k = 1 toK′ Eq. 2(K − k − 1)W + floor(P/K) k = K′ + 1 to K − 1 Eq. 3(K′ − 1)W +floor(P/K) k = K

[0105] TABLE 4 Initial Midamble Offsets for Long Midambles assumes: K′ =8, K = 16, W = 57, P = 456, L = 512 k v3.3.0 v4.1.0 1 399 399 2 342 3423 285 285 4 228 228 5 171 171 6 114 114 7  57  57 8  0  0 9 427 370 10 370 313 11  313 256 12  256 199 13  199 142 14  142  85 15   85  28 16  28 427

[0106] TABLE 5 Initial Midamble Offsets for Short Midambles assumes: K′= 3, K = 6, W = 64, P = 192, L = 256 k v3.3.0 v4.1.0 1 128 128 2  64  643  0  0 4 160  96 5  96  32 6  32 160

[0107]FIG. 13 illustrates the processing timeline that corresponds tothe block diagram.

[0108] Step 1: At the beginning of Steiner processing, CHEST kicks offthe midamble cancellation preload process. During this process, midamblecancellation requests the entire basic midamble sequence from themidamble server and stores it into a local RAM.

[0109] Step 2: After post-processing is complete, CHEST kicks offmidamble cancellation main processing this process, midamblecancellation retrieves midamble samples and channel responses for eachactive midamble shift.

[0110] Step 3: At the end of processing, each PE contains 2 accumulatorsfull of data. The first accumulator from each PE (corresponding to datafield 1 results) is sequentially muxed out and stored into RAMs (See RAM82 and 84—FIG. 7). Next, the second accumulator (data field 2 results)from each processing element is muxed out sequentially and stored (RAMs86 and 88).

[0111] Steps 4, 5: If the number of processing elements is less thanW-1, steps 2 and 3 are repeated until all of the required processing iscomplete.

[0112] The following is a description of the processing flow and thefinite state machines that control various processes within the midamblecancellation function.

[0113]FIG. 14 illustrates the processing that takes place for themidamble cancellation function. This is similar to the processingtimeline shown in FIG. 13, but breaks down the control processesrequired.

[0114] There are two (2) control signals that start MDC processing. Thefirst signal starts the MDC preload process (S1). The second controlsignal kicks off the MDC main processing (S2).

[0115] The available processing elements (PEs) are each assigned toprocess one row of the matrix multiplication (S3). If the total numberof PE's is less than the total number of rows (W-1), then the PE's willbe assigned to a first set of rows. Once processing is complete for thisset of rows, the PE's will be reassigned to the next set of rows. Thisis repeated until all of the rows have been processed.

[0116] The next step is to loop through each midamble shift in order tolook for an active midamble (S4). When an active shift is found, thematrix multiplication continues (S5).

[0117] The multiplication continues for the entire midamble sequence forthe current shift. This continues until all midamble shifts have beenprocessed. Once all of the active midamble shifts have been processed(S6), data is available for both data field 1 and data field 2 (S7). Thedata is sequentially output and written into the output RAMs.

[0118] The entire process is repeated until all W-1 rows are processed(S8).

[0119] The state machines, shown in FIGS. 15 through 20, control theprocesses depicted in the flowchart of FIG. 16.

[0120] The preload state machine, FIG. 15, requests the current midamblenumber from the midamble server and stores the data into a local RAM.The process is complete when the entire sequence is stored.

[0121] The preprocessor, FIG. 16, sequences through the active midambleparameter in order to count up the total number of active midambles thatneed to be processed.

[0122] The processing element state machine, FIG. 17, keeps track of thenumber of rows that have been processed and which PE's are assigned toeach row. This state machine continues processing until all rows of themidamble cancellation matrix have been processed.

[0123] The midamble shift state machine, FIG. 18, sequences through eachmidamble shift in order to process each active shift. As the shiftnumber is incremented, this state machine checks whether the currentshift is active or not. If the midamble shift is active, the data packerstate machine is kicked off in order to retrieve the midamble data. Onceall of the midamble shifts have been processed, this state machine kicksoff the data output state machine.

[0124] The midamble data packer state machine, FIG. 19, is responsiblefor retrieving midamble data from the local RAM and packing it into16-bit words. The order in which the data is retrieved from RAM is basedon the current midamble shift.

[0125] The data output state machine, FIG. 20, is responsible forwriting the midamble cancellation output data sequentially into RAM. Allof the data field 1 results are written first. The data field 2 resultsare written next.

[0126] The internal bit widths were chosen to accommodate the followingmaximum parameters:

[0127] maximum number of PE's=64

[0128] maximum W=114 TABLE 6 Table of Processing Times for VariousParameters K = 4  K = 8  K = 16 K = 3  K = 6  NPEs W = 114 W = 57 W = 29W = 64 W = 32 16 4427 2221 1135 1013 511 32 2380 1181  610  578 295 481887 1205  610  581 295 64 1397  715  610  365 295

[0129] Table 6 lists the number of clock cycles required to performmidamble cancellation for the given parameters. The measurements weretaken from the start of processing, excluding the midamble preload fromthe midamble server.

What is claimed is:
 1. A method for parallel midamble cancellation in aTDD burst for canceling the effect of midamble interference fromcorresponding parts of the received burst, comprising: a) receiving andstoring the received burst; b) determining a channel estimation from amidamble portion of a received burst; c) utilizing the channelestimation for obtaining channel responses in midamble shift numbers; d)utilizing the channel responses, midamble shift numbers and the receivedburst for canceling the effect of midamble interference on the receivedburst, which includes data parts, midamble, and the guard interval,whereby the midamble interference on a received burst comprised of adata field 1, a midamble and a data field 2, is cancelled from the databurst.
 2. The method of claim 1 wherein the cancellation procedureincludes employing the channel responses and midamble shifts toconstruct midamble interference on the convoluted tail of data field 1protruding into the midamble field and midamble interference on thefirst W-1 chips of the data field
 2. 3. The method of claim 2 whereinthe midamble interference obtained in step (d) are consecutivelysubtracted from a received data burst which is temporarily stored duringthe performance of step (a).
 4. A method for parallel midamblecancellation, comprising: storing a burst including at least data partsand a midamble; constructing midamble interference on a convolution tailof a first one of the data parts protruding on to the midamble fieldresponsive to channel responses and midamble shift numbers; constructingmidamble interference on a first group of chips of a second part of thedata field responsive to said midamble shift numbers and channelresponses; subtracting the midamble interference from a first number ofchips of the midamble field of the data burst to provide an intermediateresult; and subtracting the midamble interference from a first givennumber of chips of the second part of the data field from theintermediate result to provide a midamble canceled data burst.
 5. Themethod of claim 4 wherein the midamble shift numbers are obtained fromconverting received midamble shifts to midamble codes.
 6. The method ofclaim 4 wherein the midamble interference of the first data partcomprises midamble interference on a convolution tail of the first datapart protruding on to the midamble field.
 7. The method of claim 4wherein the midamble interference constructed on chips of the seconddata part comprises the first W-1 chips of the second data part whereW=the number of chips.
 8. A method for midamble cancellation comprising:a) storing a midamble a multi-stage shift register having an input stageand an output stage; b) applying a value of each stage of the registerto an associated multiplier, whereby each multiplier multiplies themidamble of its associated stage with a channel response; c) separatingeach multiplier output into a real part and an imaginary part; and d)separately storing the real and imaginary parts.
 9. The method of claim8 further comprising: (e) shifting the value in each stage in a givendirection to advance the value of each stage to the multiplierassociated with the next stage responsive to each multiplicationoperation; and (f) repeating steps (b) through (d).
 10. The method ofclaim 9 wherein steps (b) through (f) are repeated until the midambleinitially placed in the input stage has reached a given stage.
 11. Themethod of claim 8 wherein the real and imaginary parts are subtractedfrom a given number of chips of a midamble field of a data burst. 12.The method of claim 8 wherein the real and imaginary parts aresubtracted from a given number of chips of a data field of a data burst.13. Apparatus for parallel midamble cancellation in a TDD burst forcanceling the effect of midamble interference from corresponding partsof the received burst, comprising: means for receiving and storing thereceived burst; means for determining a channel estimation from amidamble portion of a received burst; means for utilizing the channelestimation for obtaining channel responses and midamble shift numbers;means responsive to the channel responses, midamble shift numbers andthe received burst for canceling the effect of midamble interference onthe received burst which includes data parts, midamble, an the guardinterval, whereby the midamble interference on a received burst,comprised of a data field 1, a midamble and a data field 2, is cancelledfrom the data burst.
 14. The apparatus of claim 13 wherein thecancellation procedure includes means employing the channel responsesand midamble shifts to construct a first midamble interference on theconvoluted tail of data field 1 protruding into the midamble field and asecond midamble interference on the first W-1 chips of the data field 2.15. The apparatus of claim 14 comprising means for consecutivelysubtracting said first and second midamble interferences from the storeddata burst.
 16. Apparatus for parallel midamble cancellation,comprising: means for storing a received burst including at least dataparts and a midamble; means for constructing midamble interference on aconvolution tail of a first one of the data parts protruding on to themidamble field responsive to channel responses and midamble shiftnumbers; means for constructing midamble interference on a first groupof chips of a second part of the data field responsive to said midambleshift numbers and channel responses; means for subtracting the midambleinterference from a first given number of chips of the midamble field ofthe data burst to provide an intermediate result; and means forsubtracting the midamble interference from a first given number of chipsof the second part of the data field from the intermediate result toprovide a midamble canceled data burst.
 17. The apparatus of claim 16wherein the midamble shift numbers are obtained by means for convertingreceived midamble shifts to midamble codes.
 18. The apparatus of claim16 wherein the midamble interference of the first data part comprisesmidamble interference on a convolution tail of the first data partprotruding on to the midamble field.
 19. The apparatus of claim 16wherein the midamble interference constructed on chips of the seconddata part comprises the first W-1 chips of the second data part whereW=the number of chips.
 20. Apparatus for midamble cancellationcomprising: means for transferring a midamble into a multi-stage shiftregister; means for applying a value at each stage of the register to anassociated multiplier, whereby each multiplier multiplies the midambleof its associated stage with a channel response; means for separatingeach multiplier output into a real part and an imaginary part; and meansfor separately storing the real and imaginary parts.
 21. The apparatusof claim 20 further comprising: means for shifting the content of eachstage in a given direction to advance the content of each upstream stageto a multiplier associated with the next downstream stage.
 22. Theapparatus of claim 21 further comprising accumulating each multiplieroutput.
 23. The apparatus of claim 20 further comprising subtracting thereal and imaginary parts from a given number of chips of a midamblefield of a data burst.
 24. The apparatus of claim 20 further comprisingsubtracting the real and imaginary parts from a given number of chips ofa data field of a data burst.
 25. The apparatus of claim 20 wherein eachmultiplier comprises: an adder/subtractor for respectively adding achannel response to a total value when a midamble content is a firstbinary state and subtracting the channel response from said total valuewhere a midamble content is a second binary state; an accumulator foradding the output of the adder/subtractor to the present contents toprovide a total value; and a multiplexer for providing the total valueto the adder/subtractor for the next addition/subtraction operation. 26.The apparatus of claim 25 further comprising means for initializing theaccumulator responsive to initiation of a cancellation operation. 27.Apparatus for canceling midamble interference from a received data burstcomprised of a first and second data fields and a multi-bit midamble,said apparatus comprising: a plurality of processing elements (PE);means for obtaining channel responses and a midamble from the databurst; means for selectively coupling the channel responses to each PE;means for successively coupling each bit of said midamble to each PE;each PE including means for combining each channel response with eachmidamble bit; first and second accumulators for accumulating the outputof each PE for each channel response; and means for respectivelyremoving each value in said accumulators from said first and second datafields.
 28. The apparatus of claim 27 wherein the combining means ofeach PE comprises: an adder/subtractor for respectively adding orsubtracting an associated channel response from a given value providedto said adder/subtractor responsive to a binary state of a midamble bitcoupled to the PE; a multiplexer for selectively coupling an output ofthe adder/subtractor to one of the first and second accumulators; and amultiplexer for selectively feeding a content of one of the accumulatorsto provide said given value to the adder/subtractor.
 29. The apparatusof claim 28 further comprising means for initializing said accumulatorsto provide an initial given value preparatory to a cancellationoperation.
 30. The apparatus of claim 27 wherein said channel responseis comprised of real and imaginary components; and the combining meansof each PE comprising first and second adder/subtractors forrespectively adding or subtracting a channel response from the givenvalue.
 31. The apparatus of claim 30 wherein said first and secondadder/subtractor respectively accumulate real and imaginary components.32. The apparatus of claim 30 wherein each adder/subtractor selectivelyprocesses interference values to be respectively cancelled from thefirst and second data fields.